Stress engineering techniques are employed to improve the performance of CMOS devices by applying a mechanical stress/strain to the channel region of FETs, with pFET devices requiring compressive stress and nFET devices requiring tensile stress. The applied stress enhances the mobility of the majority carriers (holes in pFET and electrons in nFET devices), enabling higher transistor drive currents and faster logic gate switching speeds.
Several techniques have been developed for applying the mechanical strain to the channel region of the FETs. One technique involves depositing a silicon-germanium alloy on top of active regions of the FETs, wherein the larger size of the germanium atoms results in a compressive strain in the channel region. A second technique involves deposition of an overlying layer of material having a different coefficient of thermal expansion as compared to the silicon and dielectric materials (e.g. silicon dioxide) employed for STI (shallow trench isolation) in the underlying substrate, with the difference in the coefficient of thermal expansion resulting in a transfer of a mechanical strain to the underlying substrate, including the channel regions.
In CMOS technology, process variations, such as variations in the gate length and channel doping of the transistors and in the line width of metal lines, for example, result in variations in the performance of the transistors. Such performance variations can adversely impact the performance of the integrated circuits. While stress engineering techniques, including those described above, improve transistor performance, the amount of strain introduced to a channel region depends on depends on the physical layout and construction of the underlying transistors and devices (e.g. logic gates). As such, due to the layout-dependent variations in the amount of strain achieved, stress engineering techniques can further increase device-to-device variations. Consequently, even though the performance of individual transistors and the speed of individual logic gates are improved, if the increased variations are not properly accounted for, the overall performance of the integrated circuit may be adversely impacted.
One technique employed to address such layout dependency is to extensively characterize the devices and/or logic gates of the integrated circuit. This is accomplished by designing appropriate test circuits and developing an extraction algorithm based on measured results obtained from these test circuits. However, for custom and semi-custom circuits, the huge number of possible combinations of standard cell arrangements which can be employed to form such circuits requires significant effort in terms of designing and measuring test structures. As such, extraction algorithms can become very complex and required long run-times during circuit verification. Additionally, if the stress application is subjected to changes of a fabrication process or varies due to an aging mechanism, even extensive circuit characterization will leave uncertainties and the performance of transistors and logic gates will vary correspondingly.
Another technique employed to address the layout dependency is to increase or widen safety margins used during the design process to account for the impact on the circuit by the increased variations. However, widening of the safety margins detracts from the performance improvement provided by strain engineering and still requires extensive characterization of the circuit and standard cell library.